Threshold voltage (Vt) of a field effect transistor (FET) is the minimum gate-to-source voltage differential that is required to create a conducting path through the channel, and between the source and drain (S/D) terminals or regions of the FET. The Vt of devices within a semiconductor integrated circuit is one of the critical parameters that must be carefully controlled and matched from transistor to transistor for proper commercially reproducible operation. This is the case for such FET technologies as planar complementary metal-oxide semiconductor (CMOS) FETs or FinFETs, either of which may be manufactured on bulk semiconductor substrates or silicon-on-insulator (SOI) substrates.
The degree to which Vt will vary between adjacent transistors is known as Vt mismatch (Vtmm). With constant down-scaling of ultra-high density integrated circuits, the threshold for acceptable Vtmm is also scaled down. Therefore Vtmm becomes increasingly problematic for lower scale semiconductor technology class sizes, such as the 14 nanometers (nm) node and beyond. This is particularly the case in technologies, such as static random access memory (SRAM) technology, where transistor pairs have to be closely matched for proper operation.
Two major contributors to Vtmm in a FET are the geometry of the FET's gate stack (e,g, the critical dimensions, or gate work-function metal layer thickness) and the degree of random diffusion of dopants in the FET's channel. With regards to a FET's gate stack geometry and structure, an ideal gate stack would have a perfectly square geometry, vertical profile, and a perfectly uniform thickness of layers in the gate stack with its bottom layer being a perfectly uniformly thick high-k gate dielectric layer. The high-k dielectric layer, in turn, would be disposed flat against the FET's channel. However, this is hard to consistently achieve from device to device, especially at smaller critical dimensions (CD), wherein most gate stacks will tend to have bottom corner regions that are variously rounded from device to device. Additionally, the gate stacks of smaller CD devices tend to be variously thicker in the rounded corner regions than in the middle portions of the gate stacks. As a result, the well-known effective work function of the gate stacks (i.e., the gate dielectric layer, the gate work-function metal layer, and other gate electrode layers) of scaled devices will tend to vary across the channel regions of such devices. Because the effective work function of a device directly affects that device's Vt, than the more the effective work function varies between devices in an integrated circuit, the greater the Vtmm between those adjacent devices will be.
This is particularly the case with replacement metal gate (RMG) transistor technologies, wherein a metal gate stack (which generally includes a gate work-function metal layer and a gate electrode metal disposed over a gate dielectric layer) is used to replace a polysilicon dummy gate. More particularly, this is especially problematic with RMG FETs having titanium nitride (TiN) as a gate work-function metal layer.
With regards to the amount of random diffusion of dopants in a FET's channel, a major contributor to such random diffusion of dopants is the excessive use of annealing processes, such as rapid thermal annealing (RTA), during device formation. Other major contributors to random dopant diffusion into a FET's channel include dopant implantation within the S/D regions, lightly doped drain (LDD) implants within the channel and Halo (or pocket) implants within the channel.
However, each of the above listed features that contribute to increased diffusion of dopants into the channel are utilized to address specific problems or provide specific benefits, during the formation of a FET, making those features difficult to eliminate or replace. For example, S/D dopant implantation is often required to enhance conductivity between the source and drain terminals when a FET is in the on-state. Moreover, annealing is often required to repair damage caused by ion bombardment during dopant implantation, especially in the S/D regions. Additionally, LDD implants are used to suppress short channel effects (SCEs) such as hot carrier injection, drain induced barrier lowering or the like, which become more prevalent at scaled devices. Also, Halo implants are used to reduce punch-through leakage current between source and drain, which become increasingly problematic at lower class sizes.
Accordingly, there is a need for a method and apparatus to minimize Vtmm in transistors of an integrated circuit that can be applied to such technologies as CMOS FET and finFET on either bulk or SOI substrates. In particular, there is a need to minimize Vtmm for such technologies as SRAM, where transistor pair matching is critical.
Moreover, there is a need to minimize Vtmm even if the gate stack includes rounded corners that vary from the ideal square geometry. In particular there is need to minimize Vtmm in RMG transistors having variously rounded corners in their gate stack.
Additionally, there is a need to minimize Vtmm by reducing or eliminating such formation processes as annealing and/or S/D dopant implantation while still maintaining robust source to drain conductivity when the FET is in an on-state. Further there is a need to minimize Vtmm by eliminating LDD implants while still suppressing SCEs. Also there is a need to minimize Vtmm by eliminating Halo implants while still suppressing source to drain punch-through leakage current.